1. Field of the Invention
The present invention relates to a semiconductor device.
2. Related Art
For power saving of a semiconductor device such as a processor, it is effective to change a voltage at multiple levels according to a processing load imposed on the semiconductor device such as the processor. Namely, it is effective to change a threshold of a gate electrode of a transistor by controlling a voltage (a back bias) to be applied to a region in the semiconductor device in which region the transistor is provided.
Further, a plurality of regions having different functions are often provided in the semiconductor device such as the processor. It is required to control a threshold of a gate electrode of a transistor for each region. Also in this case, similarly to the above, it is effective to change the threshold of the gate electrode of the transistor by controlling the voltage applied to the region in which the transistor is provided.
There is disclosed a conventional semiconductor device in Japanese Laid-Open patent publication No. 7-58289. FIG. 12 is a cross-sectional view that depicts a transistor formation region of this conventional semiconductor device. Two deep N-wells 5a and 5b into which N type impurities are deeply diffused are formed in a semiconductor substrate 3. A P-well 6a and an N-well 7a are formed in the deep N-well 5a, and a digital circuit (not shown) of a CMOS configuration is formed thereon. The N-well 7a is connected to a digital power supply VDD through a high concentration impurity layer N+. A P-well 6b and an N-well 7b are formed in the N-well 5b, and an analog circuit (not shown) of a CMOS configuration is formed thereon. The N-well 7b is connected to an analog power supply VDD through a high concentration impurity layer N+.
Two N-type high concentration impurity regions N+ and one P-type high concentration impurity region P+ are formed in a P-well 4 formed at a surface of the P-type substrate 3. The P-well 4 is positioned between a region in which the digital circuit is formed (hereinafter, “digital circuit region”) and a region in which the analog circuit is formed (hereinafter, “analog circuit region”). One of the two N-type impurity regions N+ is connected to the digital power supply VDD whereas the other N-type impurity region N+ is connected to the analog power supply VDD. The P-type impurity region P+ is connected to a grounding power supply (not shown) through a substrate-dedicated grounding terminal GND, and the P-well 4 serves as a grounding region.
According to the Japanese Laid-Open patent publication No. 7-58289, with this configuration, the digital circuit region and the analog circuit region serve as a triple-well transistor formation region including the deep N-wells, respectively. This transistor formation region electrically isolates the digital circuit from the analog circuit, thereby suppressing an electrical interference between the digital and analog circuits.
There is also disclosed another conventional semiconductor device in WO 2004/061967. FIG. 13 is a plan view for describing a configuration of the semiconductor device disclose in the WO 2004/061967. Namely, FIG. 13 is a top view that depicts a plurality of N-well (e.g., N-well_1 and N-well_2) and a plurality of oblique deep N-well regions (DDNWs) that form a mesh transistor formation region. The oblique deep N-well regions 410A and 410B are orthogonal to the oblique deep N-well regions 412A, 412B, and 412C. The oblique deep N-well regions 412A, 412B, 412C, 410A, and 410B form a mesh transistor formation region 490. A body bias potential Vnw is distributed to the N-wells N-well_1 and N-well_2, thereby applying the body bias to PFETs 470.
A direction of the mesh transistor formation region 490 is oblique to a direction of the N-well_1 and N-well_2. The mesh transistor formation region 490 forms an angle of 45 degrees with respect to a plurality of N-wells (e.g., N-well_1 and N-well_2). The respective oblique deep N-well regions 412A, 412B, 412C, 410A, and 410B are linear, doped with N-impurities, and provided below the N-well_1 and N-well_2 in the semiconductor device.
According to the conventional technique disclosed in the Japanese Laid-Open patent publication No. 7-58289, however, since a plurality of island-type N-wells are provided in the sea-like P-substrate, it is disadvantageously difficult to integrally adjust well potentials of the N-wells. As a result, it is disadvantageously difficult to integrally adjust thresholds of gate electrodes of PMOS circuits in the N-wells. To enable to integrally adjust the potentials of a plurality of N-wells, it is necessary to additionally provide metal interconnections among the N-wells. This disadvantageously complicates an interconnect layout and increases a chip area.
According to the conventional technique disclosed in the WO 2004/061967, a noise tends to be propagated among a plurality of regions having different characteristics. Namely, in this semiconductor device, the mesh transistor formation region 490 that supplies the body bias (back bias) to the N-well_1, N-well_2, P-well, and the like is formed. Due to this, if a plurality of regions having different characteristics and including a digital circuit, an analog circuit, and the like are formed in the N-well_1, N-well_2, and P-well on the mesh transistor formation region 490, respectively, the noise tends to be propagated among the regions having different characteristics through the deep N-well regions 412A, 412B, 412C, 410A, and 410B that supply potentials to the N-well_1, N-well_2, and the like.